WGU C952 CH5 Vocabulary Already Passed

WGU C952 CH5 Vocabulary Already Passed Combinational Element ✔✔an operational element ex: AND gate, ALU State Element ✔✔memory element ex: register or memory Clocking Methodology ✔✔the approach used to determine wh ...

WGU C952 CH5 Vocabulary Already Passed Combinational Element ✔✔an operational element ex: AND gate, ALU State Element ✔✔memory element ex: register or memory Clocking Methodology ✔✔the approach used to determine when data is valid and stable relative to the clock Edge-Triggered clocking ✔✔a clocking scheme in which all state changes occur on a clock edge make reading and writing in same cycle possible control signal ✔✔a signal used for multiplexor selection or for directing operation of a functional unit contrasts with data signal which contains information that is operated on by a functional unit Asserted ✔✔the signal is logically high or true deasserted ✔✔the signal is logically low or false Datapath Element ✔✔a unit used to operate on or hold data within a processor LEGv8 implementation = ______ include the instruction and data memories, the register file, the ALU, and adders Register File ✔✔a state element that consists of a set of registers that can be read and written by supplying a register to be accessed Sign-Extend ✔✔to increase the size of a data item by replicating the high-order sign bit of the original data item in the high-order bits of the larger, destination data item Branch Target Address ✔✔the address specified in a branch -> new program counter if the branch is taken LEGv8 [branch target = offset field + address of branch] branch taken ✔✔all unconditional branches are these causes the PC to become the branch target branch not taken ✔✔causes the PC to become the address of the address that sequentially follows Don't-care item ✔✔an element of a logical function in which the output does not depend on the values of all the inputs may be specified in different ways single-cycle implementation (single clock cycle implementation) ✔✔simple but too slow to be practical Structural Hazard ✔✔when a planned instruction cannot execute in the proper clock cycle because the hardware does not support combination set to execute Data Hazard (Pipeline Data Hazard) ✔✔when a planned instruction cannot execute in the proper clock cycle because data that is needed to execute are not yet available Forwarding (bypassing) ✔✔a method of resolving a data hazard retrieve missing data element from internal buffers Load-Use Hazard ✔✔a specific form of data hazard the data being loaded by a load instruction has not yet become available when it is needed by another instruction Pipeline Stall (Bubble) ✔✔stall initiated in order to resolve a hazard Control Hazard (Branch Hazard) ✔✔when the proper instruction cannot execute in the proper pipeline clock cycle because the instruction that was fetched is not the one that is needed the flow of instruction addresses is not what the pipeline expected Branch Prediction ✔✔a method of resolving a branch hazard that assumes a given outcome for the conditional branch and proceeds from the assumption rather than waiting to ascertain the actual outcome Latency (pipeline) ✔✔the number of stages in a pipeline or the number of stages between two instructions during execution nop ✔✔an instruction that does no operation to change state Flush ✔✔to discard instructions in a pipeline, usually due to an unexpected event Branch Prediction Buffer (Branch History Table) ✔✔a small memory that is indexed by the lower portion of the address of the branch instruction and that contains one or more bits indication whether the branch was recently taken or not Branch Target Buffer (BTB) ✔✔a structure that caches the destination PC or destination instruction for a branch usually organized as a cache with tags => costly Correlating Predictor ✔✔branch predictor that combines local behavior of a particular branch and global information about the behavior of some recent number of executed branches Tournament Branch Predictor ✔✔a branch predictor with multiple predictions for each branch and a selection mechanism that chooses which predictor to enable for a given branch Vectored Interrupt ✔✔an interrupt for which the address to control is transferred is determined by the cause of the exception Imprecise Interrupt ✔✔interrupts or exceptions in pipelined computers that are not associated with the exact instruction that was the cause Precise Interrupt ✔✔an interrupt or exception that is always associated with the correct instruction in pipelined computers Instruction-level parallelism (ILP) ✔✔The parallelism among instructions. multiple issue ✔✔a scheme whereby multiple instructions are launched in one clock cycle static multiple issue ✔✔an approach to implementing a multiple-issue processor where many decisions are made by the compiler before execution dynamic multiple issue ✔✔an approach to implementing a multiple-issue processor where many decisions are made during execution by the processor issue slots ✔✔the positions from which instructions could issue in a given clock cycle correspond to positions at the starting block