ECE 563 Solutions - North Carolina State University ECE 563 2022

ECE463/563 – Microprocessor Architecture Homework #1 Problem 1 [10 points] Answer the following questions. In all cases, show how you obtained the result. 1. Assume to include in a processor a new fast floating-point ...

ECE463/563 – Microprocessor Architecture Homework #1 Problem 1 [10 points] Answer the following questions. In all cases, show how you obtained the result. 1. Assume to include in a processor a new fast floating-point unit that speeds up floating-point operations by an average factor 2×. In addition, assume that floating-point operations take 20% of the original program execution. What is the overall speedup? [3 points] Apply Amdahl’s law with fENH=20%, sENH=2. Speedup = 1/(0.8+0.2/2) = 1.11 2. Assume that speeding up the floating-point operations causes a slow down in the data cache accesses. For example, given the additional space taken by the more sophisticated floating-point unit, memory operations take some extra cycles to get to the cache. Specifically, assume that data cache accesses, which consume 10% of the original program execution time, are now slowed down by a factor 1.5×. What is the overall speedup? [3 points] Exec-timeNEW = Exec-timeOLD (0.2 x 1/2 + 0.1 x 1.5 + 0.7) Speedup = Exec-timeOLD/Exec-timeNEW =1/(0.2 x 1/2 + 0.1 x 1.5 + 0.7) = 1.05 3. After implementing the new floating-point unit, what percentage of the execution time is spent on floatingpoint operations and what percentage is spent on data cache accesses? [4 points] FP = 0.1/0.95 ~ 10.5% Memory = 0.15/0.95 ~ 15.8% Page 2 of 9 ECE463-563 Spring 2022 Problem 2 [30 points] What would be the expected outcome of the following instructions? [2+2 points] I1: BEQZ R1 #loop If value of register R1 is equal to 0, then go to instruction at label #loop. In other words: if (R1==0) NPC = NPC + #loop I2: ADD 4(R1) R2 R3 (the first operand is the destination, and the second and third operands are source operands) The sum of the values of registers R2 and R3 is stored in memory at address (value of R1 + 4). In other words: Memory[value of (R1)+4] = value of R2 + value of R3 Can the MIPS datapath below handle instructions I1 and I2? [26 points] If yes, explain how. Specifically: - Highlight the data lines relevant to each instruction. - Indicate the data carried by all the highlighted data lines, the values stored in the relevant special purpose registers, and the values of the control lines of the three multiplexers. If not, explain why and how you would modify the datapath to support each instruction.