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COMPE 270 Digital Systems: Final Exam Department of Electrical and Computer Engineering San Diego State University

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COMPE 270 Digital Systems: Final Exam Department of Electrical and Computer Engineering San Diego State University Fall 2020 First name__________________ Last name__________________ Red ID#_____ ... _______________ 1. Complete the timing diagram for ? and ? in the logic circuit below. The propagation delay of each logic gate is shown inside the gate symbol. (10 points) Page 2/8 2. Complete the timing diagram for the following circuit. Note that the initial values of ?1 and ?2 are 0. (10 points) Page 3/8 3. In this question, you will need to design a sequential counter that counts your own Red ID number (Be careful, you will need to use your own Red ID number in this question. Using others’ solutions will result in a complete false answer, which will in turn lead to a complete failure in this exam). 3.1 We plan to display your counted Red ID number using seven segment LED display that contains 7 LEDs. Each LED is called a segment and they are identified as (a, b, c, d, e, f, g) segments as shown below: Figure 1. Segments of LED display. To display a single decimal digit represented by 4 binary numbers ?, ?, ?,?, we use a 7447 decoder as shown below. For example, if ???? = 0000, the output of the decoder should be ??????? = 1111110 so that a “0” pattern is displayed in the LED segments; if ???? = 0001, the output of the decoder should be ??????? = 0110000 so that a “1” pattern is displayed in the LED segments. We are only interested in displaying decimal numbers ranging from 0 to 9 in this device. [Show More]

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