Electrical Engineering > QUESTIONS & ANSWERS > University of California, Los Angeles - EC ENGR 115CHw-05-W12-Sol (All)
University of California, Los Angeles - EC ENGR 115CHw-05-W12-Sol
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EE115C – Digital Electronic Circuits Homework #5 Solution Problem 1 – Gate Sizing with Logical Effort Consider the circuit in Figure 1. At the output of the first stage, there are 2 identicall... y sized (x) inverters. At the output of the NAND gate, there are 3 identically sized (z) inverters. Determine the scaling factors x, y, z to minimize the propagation delay from input to output. Figure 1 Solution: To minimize delay, every stage should have the same Stage Effort. √ So, , , [Show More]
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