Electronics > QUESTIONS & ANSWERS > Case Western Reserve University - EECS 314Assignment2-sol(all answers correct) (All)

Case Western Reserve University - EECS 314Assignment2-sol(all answers correct)

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TRUE or FALSE for Question1-4 and Multiple Choices for Question5. Question 1: The faster division can use parallel hardware as in multiplier. r. Question 2: The primary implementation advantage of ... fixed-length instructions is easier to pipeline since the address of the next instruction can be calculated while decoding current instruction. Question 3: Structure hazard occurs when instructions in 2 different pipeline stages (i.e. 2 different instructions) want to access the same resource in the same cycle. This hazard can be handled by duplicating the requested resource. Question 4: In the MIPS instruction set, the top 6 bits (31…26) are used for an opcode. With 6 bits, we can have 64 different combinations. This implies that the total number of instructions in the MIPS architecture should be less than 64. False. In addition to the 6-bit opcode, the R-type instructions make use of the bottom 6 bits of the instruction (the func field) to specify the ALU instruction. This allows for 26 = 64 different opcodes for the ALU instructions for each combination of the opcode bits. Question 5: (A or B) Which of the following is correct for a load instruction? Refer to the following figure. A. MemtoReg should be set to cause the data from memory to be sent to the register file; B. MemtoReg should be set to cause the correct register destination to be sent to the register file. A [Show More]

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