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University of WaterlooECE 6379-Solution_Adder

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ECE-637, Assignment - Adder Chapter 11, Digital Integrated Circuits, a Design Perspective, J. Rabaey, 2nd Edition 1) A magnitude comparator for unsigned numbers can be constructed using full adders ... and Boolean logic gates as building blocks. For this problem you are given a cell library consisting of full adders and arbitrary fan-in logic gates (i.e., AND, OR, INVERTER, etc.). a. Design an N-bit magnitude comparator with outputs A ≥ B and A = B using a minimal number of Boolean logic gates. The result of this process should be a diagram in the spirit of Figure 11.5. Specify the value of any required control signals (e.g., Cin ). Ai = Bi only if Ai - Bi = 0; For all values of Ai and Bi, if Si is 0, then Ai = Bi. If all Si signals are pass through a NOR, its output high will signify Ai = Bi. Ai - Bi = Ai + Bi′ +1 Subtraction is done using 1’s complement. If the output carry is generated, it signifies A ≥ BPage: 2 b. Express the delay of your design in computing the two outputs as a function of N, tcarry , tsum, and the Boolean gate delays (tand, tor, tinv, etc.). tA=B = tinv + (N-1)tcarry + tsum+ tNOR tA≥B = tinv + N.tcarry 2) Show how the arithmetic module in Figure P.11.1 can be used as a comparator. Derive an expression for its propagation delay as a function of the number of bits [Show More]

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