OCR GCE A LEVEL 2022 COMPUTER SCIENCE MARKSCHEMES H446-1 PAPER 1-H446/01: Computer systems

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12. Subject Specific Marking Instructions Question Answer Mark Guidance 1 (a) (i) ● Both data and instructions share the same memory ● Instructions and Data stored in same format ● A single ... set of buses / same bus for instructions & data (to connect CPU to Memory and I/O) ● Has a (single) control unit ● Has an ALU. ● Has ways to input and output. ● Has access to storage, ● Works sequentially through instructions // follows Fetch-execute cycle ● (Special) registers within CPU ● Based on stored program concept 2 (ii) ● Separate memory for data and instructions / Multiple memory units ● Different (sets of) buses one for instructions & one for data/ instructions and data can be accessed concurrently. 1 (b) ● Higher/faster clock speed ● More cores//dual/quad/etc core ● More cache memory. 2 Answers must refer to an improvement (more/higher/faster) not just “change the clock speed” Allow discussions of level 1/level 2 cache sizes for one mark. Accept valid features of CPUs that would improve performance e.g. Use of: Pipelining Simultaneous Multithreading Do not accept RISC/CISC. (c) (i) ● 10 ● 60 ● 200 3 1 mark per number H446/01 Mark Scheme June 2022 (ii) ● Loads a value into the accumulator ● Establishes a zero value (by use of DAT / SUB) ● Stores a zero value into total ● Program stops 4 Example 1 LDA zero STA total HLT zero DAT 0 Example 2 LDA total SUB total STA total HLT BP1 can be given for any value being loaded into the accumulator e.g. INP If candidate writes LDA donation/total (case sensitive) they can get BP2 as they’ve used the labels from the question BP3 - total is case sensitive as given in the question BP4 - must not be given if the zero value will be attempted to be fetched e.g. HLT is placed after DAT (iii) ● One instruction can be fetched while another is being decoded… ● …and another is executed ● The output of one process/instruction is the input of the next. ● Concurrent processing of multiple instructions // completing multiple FDE cycles at once 3 For BP1, allow any 2 of the 3 parts of the FDE cycle For BP2, must give the other part of the FDE cycle not given in BP1 Do not award if explaining multiple cores working on different parts of FDE cycle H446/01 Mark Scheme June 2022 (iv) ● More instructions can be carried out in a set amount of time // less time to execute the same number of instructions ● Increasing the speed/performance/efficiency of the computer/program // quicker for the program to complete 2 Do not allow “each instruction is quicker to execute”. BP2 has to be specific to the charity e.g. processing more donations (d) (i) ● Holds all input/output ● Holds results of calculations (from the ALU) ● Checked for conditional branching (e.g. BRZ) ● Stores data which has come from the MDR/RAM 2 (ii) ● Holds the address/location of the next instruction (to be executed/fetched) ● Contents copied to the MAR at start of FDE ● Incremented (by one) on every cycle ● Can be changed by branch/jump instructions 2 (iii) ● Memory Address Register // MAR ● Memory Data Register // MDR ● Current Instruction Register // CIR ● Index Register // IR 3 Allow Memory Buffer Register for MDR H446/01 Mark Scheme June 2022 (e) Mark Band 3–High Level (9-12 marks) The candidate demonstrates a thorough knowledge and understanding of both CISC and RISC. The material is generally accurate and detailed. The candidate is able to apply their knowledge and understanding directly and consistently to the context provided. Evidence/examples will be explicitly relevant to the explanation. The candidate provides a thorough discussion which is well balanced. Evaluative comments are consistently relevant and well-considered. There is a well-developed line of reasoning which is clear and logically structured. The information presented is relevant and substantiated. Mark Band 2-Mid Level (5-8 marks) The candidate demonstrates reasonable knowledge and understanding of CISC and/or RISC; the material is generally accurate but at times underdeveloped. The candidate is able to apply their knowledge and understanding directly to the context provided although one or two opportunities are missed. Evidence/examples are for the most part implicitly relevant to the explanation. The candidate provides a sound discussion, the majority of which is focused. Evaluative comments are for the most part appropriate, although one or two opportunities for development are missed. There is a line of reasoning presented with some structure. The information presented is in the most part relevant and supported by some evidence. 12 AO1.1 (2), AO1.2 (2), AO2.1 (3), AO3.3. (5) AO1 CISC is a complex instruction set. The traditional approach to processor design. Lots of instructions available although some instructions in CISC will rarely get used. RISC is a reduced instruction set. A smaller number of instructions available, several instructions can be combined to perform the same tasks as CISC processors. RISC instructions are used regularly. RISC has fewer transistors/less complex circuitry whereas CISC integrated circuits are more expensive/complicated. RISC instructions take one cycle whereas CISC may take several. RISC can only do complex things by combining multiple instructions whereas CISC is done in one line. Compilers for RISC need to be more complex than compilers for CISC AO [Show More]

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