CPEMBS30 – EMBEDDED SYSTEMS
Midterm Examination, 2ND Term SY 2022-2023
DIRECTION(S): READ THE INSTRUCTIONS AND FOLLOW IT VERY CAREFULLY. ERASURES AND ANY UNECESSARY MARKS TO YOUR
ANSWER WILL BE CONSIDERED A WRONG ANSW
...
CPEMBS30 – EMBEDDED SYSTEMS
Midterm Examination, 2ND Term SY 2022-2023
DIRECTION(S): READ THE INSTRUCTIONS AND FOLLOW IT VERY CAREFULLY. ERASURES AND ANY UNECESSARY MARKS TO YOUR
ANSWER WILL BE CONSIDERED A WRONG ANSWER. PLEASE CALL THE ATTENTION OF YOUR PROCTOR FOR ANY CONCERN. YOU CAN
USE THE BACK OF THE ANSWER SHEET IF NEEDED.
FILL IN THE INFORMATION ON THE BOXES BELOW. FAILURE TO COMPLY WOULD RESULT TO A 5-POINT DEDUCTION FROM YOUR TOTAL
SCORE.
Name: Date:
Section: Instructor:
I. MULTIPLE CHOICES: Write the letter of the best answer for the following questions before the number.
1. What are the steps if we will burn the saved Flowcode program to a specific PIC?
a. Compile to C-> Compile to Assembly -> Compile to Chip.
b. Compile to C -> Compile to Hex -> Compile to Chip.
c. Compile to C -> Compile to Hex -> Compile to PIC.
d. Compile to Hex -> Compile to Assembly -> Compile to PIC.
2. Which of the following does not describe the Analog to Digital Converter inside the PICmicro?
a. The highest number it can handle is determined by the resolution of the ADC inside the chip.
b. It converts information inside the PICmicro from an analogue format to a digital format.
c. Its first step is given the number 0.
d. It multiplies the range of possible analogue voltages into equal steps.
3. What are the general types of microprocessor?
a. Intel and AMD
b. Dedicated and General-purpose
microprocessors
c. 32-bit and 64-bit microprocessors
d. ASIC and Dedicated microprocessors
4. What are the main components of Von Neumann model?
a. I/O Unit, Memory, and CPU
b. ALU, Register, Data Path, and CU
c. Input, Process, and Output
d. Cache, ROM, and RAM
5. These are the division of microprocessor’s logic circuit.
a. Data Path and Control Unit
b. ALU, Register, and Control Unit
c. Register and Cache
d. Next State Logic and Output Logic
6. How does a bus formed?
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