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San Rafael HighCIS 30CSE30-HW08 (SOLUTIONS)

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A8: Sequential Logic & Processors Due: June 3, 2020 Learning Goals ● D Flip Flip & MUX Design ● Assembly code -> machine code translation ● Understanding control signals in processor Quest ... ion 1: D Flip-Flops [10 pts] A) Given the following input waveforms to a ​D Flip Flop​, assuming the ouput ​Q​ starts at ​0​, sketch the remainder of the waveform for the output ​Q​. B) Considering the circuit below on the left, assuming that ​Q​ starts at ​1​, sketch the remainder of the waveform for the output ​Q​.Question 2: MUX with NANDs [10 pts] Using only an inverter (NOT) gate and 2-input NAND gates, draw a schematic for the 2-input multiplexer represented by the equation ​out = SA + S’B​. ​Hint​: Remember De Morgan’s Law [Show More]

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