Computer Science > Lab Report > Centennial CollegeCOMP ETEC122Lab 5 - Counters (All)

Centennial CollegeCOMP ETEC122Lab 5 - Counters

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Objective: Upon completion of this lab, the student will have demonstrated the ability to: • Use Quartus II software to program an Altera FPGA (DE0-CV educational board) • Design a 4-bit VHDL c... ounter to store and display a single digit of Hexadecimal • Extend a counter design to multiple digits • Alter a counter design from hexadecimal representation to BCD representation Procedure: In this lab, you will design a counter using a behavioural VHDL model which you will use as the base for extending to an 8 bit counter. 1) Complete the VHDL template on the Submission Sheet to write the VHDL code for a 4-bit full sequence up counter with count enable, synchronous parallel load, and asynchronous clear. Figure 5-1: 4-bit Counter with count enable, synchronous parallel load, and asynchronous clear 2) Create a new Quartus II project for this lab with the following settings: a. Working directory = H:\ETEC122\LAB5 b. Project name = myCounter8 c. Top-Level Entity = myCounter8 d. Device = 5CEBA4F23C7 e. Simulation Tool = ModelSim-Altera (Format: VHDL) [Show More]

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