Problem Set 11 Answers
1. The read access delay for an I/O system is defined as the time required for the device
to acquire the requested data and prepare to start transmitting the data. The data transfer
rate for an
...
Problem Set 11 Answers
1. The read access delay for an I/O system is defined as the time required for the device
to acquire the requested data and prepare to start transmitting the data. The data transfer
rate for an I/O device is defined as the number of bytes per second that it can transmit the
acquired data. Suppose that there are two different I/O systems A and B. After a 4-second
access delay, system A transfers data at the rate of 4096 bytes per second. System B
transfers data at the rate of 5120 bytes per second after a 3-second access delay. Both
systems employ an 8-bit bus to transfer I/O data. Each system is used to transfer a series
of 15360-byte blocks of data. Answer the following questions about these systems:
a) (3) What is the minimum time interval between consecutive interrupts on system A if it
uses a DMA controller? Minimum time between consecutive interrupts = _7.75 sec_
One interrupt is generated at the conclusion of each block with DMA. The time interval
between consecutive blocks on system A is 4 + 15360/4096 = 7.75 seconds.
b) (3) What is the minimum time interval between consecutive interrupts on system B if it
uses interrupt driven I/O? Minimum time between consecutive interrupts = _195.3
micro-seconds____
One interrupt is generated for each byte with interrupt driven I/O. System B transfers
5120 bytes per second. Therefore the minimum time between consecutive interrupts =
1/5120 = 195.3 micro-seconds.
2. A certain processor consumes 500 cycles to perform the context switch required to
transfer control to the interrupt handler for an I/O device that triggers an interrupt. The
interrupt handler takes an additional 10,000 cycles to service the device request. Once the
interrupt processing is complete, another 500 cycles are required to perform the context
switch required to return from the interrupt handler back to the program that was running.
The processor’s clock rate is 6 GHz.
a) (5) What is the maximum number of requests per second that a device can generate
without causing the system to loose data?
Each interrupt requires 500 + 10000 + 500 = 11000 cycles. Therefore no more than one
request every 11000 cycles can be supported. Hence the upper limit is one request every
11000/6*10^9 = 1.833 micro-seconds per request which is 545,454 requests per second.
b) (5) Suppose that instead of using interrupts, a program running on the same processor,
polls some device (DeviceB) for requests. Assume that each polling operation takes 150
nano-seconds. If DeviceB generates 2.5 million requests per second and no other I/O is
performed, what is the maximum time that could be taken to service DeviceB without
losing data?
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