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Problem Set 7 Answers

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Problem Set 7 Answers (Assume that all branch instructions are treated as delayed branches for this problem set.) 1. The diagram below represents a degree 2 s... uperscalar version of our 5-‐stage MIPS pipelined system. The decode stage includes a buffer to hold instructions that have been decoded but cannot yet execute. The execute stage includes an integer unit and a load/store unit. The system allows both out-‐of-‐order execution and out-‐of-‐order completion. Each stage requires 1 clock cycle. a) (5) How many clock cycles does the following short instruction sequence consume on this superscalar system? 1. add $5,$4,$3 2. lw $2,16($6) 3. sw $9,8($7) 4. lw $10,48($12) After the first two instructions are fetched and decoded, they can execute in parallel on the two execution units. However the final sw and lw must execute sequentially since they both require the load/store unit. Hence the first two instructions complete in cycle 5, the sw completes in cycle 6 and the lw completes in cycle 7. b) (3) How many clock cycles does the same instruction sequence consume on the original 5- stage scalar system? On the original scalar system, the sequence would require 8 cycles. The add completes in cycle 5 with one additional cycle required for each of the remaining 3 instructions. c) (3) How many read ports are required for the register file to support the superscalar system? Recall that a separate read port is required for each register input operand. Since this is a degree 2 superscalar system, up to 2 instructions may have to read a pair of input registers at the same time, so 4 register read ports are required. [Show More]

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