Electrical and Computer Engineering, Purdue University Northwest
Computer Organization and Design (ECE 37100), Spring 2020
Lab Assignment: 8, Total Points: 100, Due Date: April 30, 2020 (Thursday)
Textbook Sections: D
...
Electrical and Computer Engineering, Purdue University Northwest
Computer Organization and Design (ECE 37100), Spring 2020
Lab Assignment: 8, Total Points: 100, Due Date: April 30, 2020 (Thursday)
Textbook Sections: Digital Design and Computer Architecture: 7.3, Appendix B for machine
code, and Lecture 5 Slides
Acknowledgement: The lab assignment is adopted from authors’ website.
Introduction
In this lab, you will build a simplified ARM single-cycle processor using SystemVerilog. Then,
you will load a test program and confirm that the system works. Next, you will implement a few
new instructions, and then write new test programs that confirms the new instructions work as
well. By the end of this lab, you should thoroughly understand the internal operation of the ARM
single-cycle processor.
Before starting this lab, you should be very familiar with the single-cycle implementation of the
ARM processor. The single-cycle processor schematic from the text is repeated at the end of this
lab assignment for your convenience. This version of the ARM single-cycle processor can
execute the following instructions: ADD, SUB, AND, ORR, LDR, STR, and B.
Our model of the single-cycle ARM processor divides the machine into two major units: the
control and the datapath. Each unit is constructed from various functional blocks. For example,
as shown in the figure on the last page of this lab, the datapath contains the 32-bit ALU, the
register file, the sign extension logic, and five multiplexers to choose appropriate operands.
ARM Single-Cycle Processor
Use the ARM Single-cycle processor code given with the assignment. Study the code until you
are familiar with the contents. The top-level module (named top) contains the arm processor
(arm) and the data and instruction memories (dmem and imem). Now look at the processor
module (called arm). It instantiates two sub-modules, controller and datapath. Now
look at the controller module and its submodules. It contains two sub-modules: decoder
and condlogic. The decoder module produces all but three control signals. The
condlogic module produces those remaining three control signals that update architectural
state (RegWrite, MemWrite) or determine the next PC (PCSrc). These three signals depend
on the condition mnemonic from the instruction (Cond3:0) and the stored condition flags
(Flags3:0) that are internal to the condlogic module. The condition flags produced by the
ALU (ALUFlags3:0) are updated in the flags registers dependent on the S bit (FlagW1:0) and
on whether the instruction is executed (again, dependent on the condition mnemonic Cond3:0
and the stored value of the condition flags Flags3:0). Make sure you thoroughly understand the
controller module. Correlate signal names in the SystemVerilog code with the wires on the
schematic.
After you thoroughly understand the controller module, look at the datapath SystemVerilog
module. The datapath has quite a few submodules. Make sure you understand why each
submodule is there and where each is located on the ARM single-cycle processor schematic.
The instruction and data memories instantiated in the top module are each a 64-word × 32-bit
array. The instruction memory needs to contain some initial values representing the program. The
test program is given as memfile.s. The machine code of the test program stored in memfile.dat
is loaded into the instruction memory.
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