Computer Science > STUDY GUIDE > University of Texas, Dallas - CS 3340Oxk120030_CS_3340_HW5 (All)

University of Texas, Dallas - CS 3340Oxk120030_CS_3340_HW5

Document Content and Description Below

HW 5 – Exercises 4.2, 4.3, 4.4, and 4.7  Exercise 4.2 :( Section 4.1) The basic single-cycle MIPS implementation in Figure 4.2 can only implement some instructions. New instructions can be adde... d to an existing Instruction Set Architecture (ISA), but the decision whether or not to do that depends, among other things on the cost and complexity the proposed addition introduces into the processor datapath and control. The first three problems in this exercise refer to the new instruction: Instruction: LWI Rt , Rd( Rs ) Interpretation: Reg[ Rt ] = Mem[ Reg[ Rd ] + Reg[ Rs ] ] o 4.2.1: Which existing blocks (if any) can be used for this instruction?  Register block, the ALU, the Data memory, and the PC block o 4.2.2: Which new functional blocks (if any) do we need for this instruction?  May need to add Sign-Extend to perform load and store function on the registers to memory locations. o 4.2.3: What new signals do we need (if any) from the control unit to support this instruction?  No new signals are needed.  Exercise 4.3: (Section 4.1) When processor designers consider a possible improvement to the processor datapath, the decision usually depends on the cost/performance trade-off. In the following three problems, assume that we are starting with a data path from Figure 4.2, where I-Mem, Add, Mux, ALU, Regs, D-Mem, and Control blocks have latencies of 400 ps, 100 ps, 30 ps, 120 ps, 200 ps, 350 ps, and 100 ps, respectively, and costs of 1000, 30, 10, 100, 200, 2000, and 500, respectively. Consider the addition of a multiplier to the ALU. This addition will add 300 ps to the latency of the ALU and will add a cost of 600 to the ALU. The result will be 5% fewer instructions executed since we will no longer need to emulate the MUL instruction. o 4.3.1: What is the clock cycle time with and without this improvement?  Since Load-word is the longest path, we will calculate its clock cycle before and after the improvement:  (I-Mem)400 + (Regs)200 + (Mux)30 + (ALU)120 + (D-Mem)350 + (Mux)30 + (Regs)200 = 1330ps o Before improvement [Show More]

Last updated: 2 years ago

Preview 1 out of 4 pages

Buy Now

Instant download

We Accept: